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S29GL-N MirrorBit(R) Flash Family
S29GL064N, S29GL032N
64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL-N MirrorBit(R) Flash Family Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29GL-N_01
Revision 09
Issue Date November 16, 2007
Data
Sheet
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local sales office.
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
S29GL-N MirrorBit(R) Flash Family
S29GL064N, S29GL032N
64 Megabit, 32 Megabit 3.0 Volt-only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation Manufactured on 110 nm MirrorBit process technology Secured Silicon Sector region
- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence - Programmed and locked at the factory or by the customer
Low power consumption
- 25 mA typical active read current - 50 mA typical erase/program current - 10 A typical standby mode current
Package options
- - - - 48-pin TSOP 56-pin TSOP 64-ball Fortified BGA 48-ball fine-pitch BGA
Flexible sector architecture
- 64Mb (uniform sector models): One hundred twenty-eight 32 Kword (64 KB) sectors - 64 Mb (boot sector models): One hundred twenty-seven 32 Kword (64 KB) sectors + eight 4Kword (8KB) boot sectors - 32 Mb (uniform sector models): Sixty-four 32Kword (64 KB) sectors - 32 Mb (boot sector models): Sixty-three 32Kword (64 KB) sectors + eight 4Kword (8KB) boot sectors
Software & Hardware Features
Software features
- Advanced Sector Protection: offers Persistent Sector Protection and Password Sector Protection - Program Suspend & Resume: read other sectors before programming operation is completed - Erase Suspend & Resume: read/program other sectors before an erase operation is completed - Data# polling & toggle bits provide status - CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices - Unlock Bypass Program command reduces overall multiple-word programming time
Enhanced VersatileI/OTM Control
- All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. VIO range is 1.65 to VCC
Compatibility with JEDEC standards
- Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection
100,000 erase cycles typical per sector 20-year data retention typical
Hardware features
- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings on uniform sector models - Hardware reset input (RESET#) resets device - Ready/Busy# output (RY/BY#) detects program or erase cycle completion
Performance Characteristics
High performance
- - - - 90 ns access time 8-word/16-byte page read buffer 25 ns page read time 16-word/32-byte write buffer which reduces overall programming time for multiple-word updates
Publication Number S29GL-N_01
Revision 09
Issue Date November 16, 2007
Data
Sheet
General Description
The S29GL-N family of devices are 3.0-Volt single-power Flash memory manufactured using 110 nm MirrorBit technology. The S29GL064N is a 64-Mb device organized as 4,194,304 words or 8,388,608 bytes. The S29GL032N is a 32-Mb device organized as 2,097,152 words or 4,194,304 bytes. Depending on the model number, the devices have 16-bit wide data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The devices can be programmed either in the host system or in standard EPROM programmers. Access times as fast as 90 ns are available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and the Ordering Information-S29GL032N, and Ordering Information-S29GL064N. Package offerings include 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0-Volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. The Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection is a method that replaces the previous 12-volt controlled protection method. Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted. Device programming and erasure are initiated through command sequences. Once a program or erase operation begins, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/ Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses are stable for a specified period of time. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin or WP# pin, depending on model number. The protected sector is still protected even during accelerated programming. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2. 3. 4. 5. 6. 7. 8. Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ordering Information-S29GL032N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Information-S29GL064N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 Advanced Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 Persistent Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 Persistent Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14 Password Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.15 Password and Password Protection Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 64-bit Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 Persistent Protection Bit Lock (PPB Lock Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.19 Write Protect (WP/ACC#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.20 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 17 17 18 19 19 19 19 29 30 30 31 31 33 34 34 34 35 35 36 36
9. 10.
Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Enter/Exit Secured Silicon Sector Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Program Suspend/Program Resume Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.8 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.9 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.12 RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.13 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.14 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.15 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.16 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.17 DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.18 DQ1: Write-to-Buffer Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 41 42 42 46 47 48 50 51 55 55 56 57 58 59 59 59 60
11. 12.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
November 16, 2007 S29GL-N_01_09
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13. 14. 15. 16. 17.
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 TS048--48-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 17.2 TS056--56-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 17.3 VBK048--Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package . . . . . . . . . . . . . . 17.4 LAA064--64-Ball Fortified Ball Grid Array (BGA) 13 x 11 mm Package . . . . . . . . . . . . . . . . 74 74 75 76 77
18.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
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Sheet
Figures
48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 56-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 64-ball Fortified BGA (LAA 064) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 48-ball Fine-pitch BGA (VBK 048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 S29GL064N Logic Symbol (Models 01, 02, V1, V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.2 S29GL064N Logic Symbol (Models 03, 04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.3 S29GL064N Logic Symbol (Models 06, 07, V6, V7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.4 S29GL032N Logic Symbol (Models 01, 02, V1, V2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.5 S29GL032N Logic Symbol (Models 03, 04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.1 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 10.2 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 10.3 Program Suspend/Program Resume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 10.4 Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 10.5 Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 10.6 Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 11.2 Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 14.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 14.2 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 15.1 VCC Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 15.2 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 15.3 Page Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 15.4 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 15.5 Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Figure 15.6 Accelerated Program Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 15.7 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Figure 15.8 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Figure 15.9 Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 15.10 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 15.11 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . .72 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 5.1
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
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Data
Sheet
Tables
Table 6.1 Table 7.1 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 13.1 Table 14.1 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 16.1 S29GL032N Ordering Options (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 S29GL064N Valid Combinations (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 S29GL032N (Models 01, 02, V1, V2) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 S29GL032N (Model 03) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 S29GL032N (Model 04) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 S29GL064N (Models 01, 02, V1, V2) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 S29GL064N (Model 03) Top Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 S29GL064N (Model 04) Bottom Boot Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 S29GL064N (Models 06, 07, V6, V7) Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Command Definitions (x16 Mode, BYTE# = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Sector Protection Commands (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Command Definitions (x8 Mode, BYTE# = VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Sector Protection Commands (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 DC Characteristics, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Alternate CE# Controlled Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . .71 TSOP Pin and BGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
1.
Product Selector Guide
Part Number Speed Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page Access Time (ns) Max. OE# Access Time (ns) VCC = 2.7-3.6 V VIO = 2.7-3.6 V VIO = 1.65-3.6 V 90 90 25 25 S29GL064N 90 110 110 110 30 30 90 90 25 25 S29GL032N 90 110 110 110 30 30
2. Block Diagram
RY/BY# VCC VSS Sector Switches
DQ15-DQ0 (A-1)
Erase Voltage Generator RESET#
Input/Output Buffers
WE# WP#/ACC BYTE#
State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB
Y-Decoder
Y-Gating
Timer
Address Latch
VCC Detector
X-Decoder
Cell Matrix
AMax**-A0
Note **AMAX GL064N = A21, GL032N = A20.
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
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Data
Sheet
3.
Connection Diagrams
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Figure 3.1 48-Pin Standard TSOP
S29GL064N, S29GL032N (Models 03, 04 only) S29GL064N (Models 06, 07, V6, V7 only)
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RESET# ACC WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 VIO VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
NC on S29GL032N
Figure 3.2 56-Pin Standard TSOP
NC on S29GL032N
NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
S29GL064N, S29GL032N (Models 01, 02, V1, V2 only)
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
Figure 3.3 64-ball Fortified BGA (LAA 064)
S29GL064N, S29GL032N (Models 01, 02, 03, 04, V1, V2 only) Top View, Balls Facing Down NC on S29GL032N NC on 03, 04 options
A8 NC A7 A13 A6 A9 A5 WE# A4
B8 NC B7 A12 B6 A8 B5 RESET# B4
C8 NC C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 NC
D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 NC
E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 NC
F8 NC F7 BYTE# F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO
G8 NC G7 DQ15/A-1 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 NC
H8 NC H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 NC
RY/BY# WP#/ACC A3 A7 A2 A3 A1 NC B3 A17 B2 A4 B1 NC
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
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Data
Sheet
Figure 3.4 48-ball Fine-pitch BGA (VBK 048)
S29GL064N, S29GL032N (Models 03, 04 only) Top View, Balls Facing Down
NC on S29GL032N
A6 A13 A5 A9 A4 WE# A3
B6 A12 B5 A8 B4 RESET# B3
C6 A14 C5 A10 C4 A21 C3 A18 C2 A6 C1 A2
D6 A15 D5 A11 D4 A19 D3 A20 D2 A5 D1 A1
E6 A16 E5 DQ7 E4 DQ5 E3 DQ2 E2 DQ0 E1 A0
F6 BYTE# F5 DQ14 F4 DQ12 F3 DQ10 F2 DQ8 F1 CE#
G6 DQ15/A-1 G5 DQ13 G4 VCC G3 DQ11 G2 DQ9 G1 OE#
H6 VSS H5 DQ6 H4 DQ4 H3 DQ3 H2 DQ1 H1 VSS
RY/BY# WP#/ACC A2 A7 A1 A3 B2 A17 B1 A4
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
4.
Pin Descriptions
Pin A21-A0 A20-A0 DQ7-DQ0 DQ14-DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC ACC WP# RESET# RY/BY# BYTE# VCC VIO VSS NC Description 22 Address inputs (S29GL064N) 21 Address inputs (S29GL032N) 8 Data inputs/outputs 15 Data inputs/outputs DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) Chip Enable input Output Enable input Write Enable input Hardware Write Protect input/Programming Acceleration input Acceleration input Hardware Write Protect input Hardware Reset Pin input Ready/Busy output Selects 8-bit or 16-bit mode 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Output Buffer Power Device Ground Pin Not Connected Internally
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
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Data
Sheet
5.
Logic Symbols
Figure 5.1 S29GL064N Logic Symbol (Models 01, 02, V1, V2)
22 A21-A0 DQ15-DQ0 (A-1) 16 or 8 22 A21-A0 DQ15-DQ0 (A-1) 16 or 8
Figure 5.2 S29GL064N Logic Symbol (Models 03, 04)
CE# OE# WE# WP#/ACC RESET# VIO BYTE#
CE# OE# WE# WP#/ACC RESET#
RY/BY#
BYTE#
RY/BY#
Figure 5.3 S29GL064N Logic Symbol (Models 06, 07, V6, V7)
22 A21-A0 DQ15-DQ0 CE# OE# WE# WP# ACC RESET# VIO RY/BY# 16
Figure 5.4 S29GL032N Logic Symbol (Models 01, 02, V1, V2)
21 A20-A0 DQ15-DQ0 (A-1) 16 or 8 21
Figure 5.5 S29GL032N Logic Symbol (Models 03, 04)
A20-A0 DQ15-DQ0 (A-1) 16 or 8
CE# OE# WE# WP#/ACC RESET# VIO BYTE#
CE# OE# WE# WP#/ACC RESET#
RY/BY#
BYTE#
RY/BY#
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
6.
Ordering Information-S29GL032N
S29GL032N Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
S29GL032N
90
T
A
I
01
0 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel MODEL NUMBER 01 = x8/x16, VCC= VIO = 2.7 - 3.6 V, Uniform sector, WP#/ACC = VIL protects highest addressed sector 02 = x8/x16, VCC = VIO = 2.7 - 3.6 V, Uniform sector, WP#/ACC = VIL protects lowest addressed sector 03 = x8/x16, VCC = 2.7 - 3.6 V, Top boot sector, WP#/ACC = VIL protects top two addressed sectors 04 = x8/x16, VCC = 2.7 - 3.6 V, Bottom boot sector, WP#/ACC = VIL protects bottom two addressed sectors V1 = x8/x16, VCC = 2.7 - 3.6 V, VIO = 1.65 - 3.6 V, Uniform sector, WP#/ACC = VIL protects highest addressed sector V2 = x8/x16, VCC = 2.7 - 3.6 V, VIO = 1.65 - 3.6 V, Uniform sector, WP#/ACC = VIL protects lowest addressed sector TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE MATERIAL SET A = Standard (Note 4) F = Pb-Free PACKAGE TYPE T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package F = Fortified Ball-Grid Array Package SPEED OPTION See Product Selector Guide and Valid Combinations (90 = 90 ns, 11 = 110 ns)
DEVICE NUMBER/DESCRIPTION S29GL032N 32 Megabit Page-Mode Flash Memory Manufactured using 110 nm MirrorBit(R) Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 6.1 S29GL032N Ordering Options (Note 4)
S29GL032N Valid Combinations Device Number Speed Option 90 TFI 11 90 FFI S29GL032N 11 TFI 90 BFI FFI Notes 1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3. 2. TSOP package marking omits packing type designator from ordering part number. 3. BGA package marking omits leading S29 and packing type designator from ordering part number. 4. Contact local sales for availability for Leaded lead-frame parts. 03, 04 V1, V2 V1, V2 01, 02 0,2,3 (Note 1) TS048 (Note 2) VBK048 (Note 3) LAA064 (Note 3) TSOP Fine-Pitch BGA Fortified BGA LAA064 (Note 3) Fortified BGA Package, Material, & Temperature Range Model Number 01, 02 TS056 (Note 2) TSOP Packing Type Package Description (Notes)
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
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Data
Sheet
7.
Ordering Information-S29GL064N
S29GL064N Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
S29GL064N
90
T
A
I
02
2 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel MODEL NUMBER 01 = x8/x16, VCC = VIO = 2.7 - 3.6 V, Uniform sector, WP#/ACC = VIL protects highest addressed sector 02 = x8/x16, VCC = VIO = 2.7 - 3.6 V, Uniform sector, WP#/ACC = VIL protects lowest addressed sector 03 = x8/x16, VCC = 2.7 - 3.6 V, Top boot sector, WP#/ACC = VIL protects top two addressed sectors 04 = x8/x16, VCC = 2.7 - 3.6 V, Bottom boot sector, WP#/ACC = VIL protects bottom two addressed sectors 06 = x16, VCC = 2.7 - 3.6 V, Uniform sector, WP# = VIL protects highest addressed sector 07 = x16, VCC = 2.7 - 3.6 V, Uniform sector, WP# = VIL protects lowest addressed sector V1 = x8/x16, VCC = 2.7 - 3.6 V, VIO = 1.65 - 3.6 V, Uniform sector, WP#/ACC = VIL protects highest addressed sector V2 = x8/x16, VCC = 2.7 - 3.6 V, VIO = 1.65 - 3.6 V, Uniform sector, WP#/ACC = VIL protects lowest addressed sector V6 = x16, VCC = 2.7 - 3.6 V, VIO = 1.65 - 3.6 V, Uniform sector, WP# = VIL protects highest addressed sector V7 = x16, VCC = 2.7 - 3.6 V, VIO = 1.65 - 3.6 V, Uniform sector, WP# = VIL protects lowest addressed sector TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE MATERIAL SET A = Standard (Note 4) F = Pb-Free PACKAGE TYPE T = Thin Small Outline Package (TSOP) Standard Pinout B = Fine-pitch Ball-Grid Array Package F = Fortified Ball-Grid Array Package SPEED OPTION See Product Selector Guide and Valid Combinations (90 = 90 ns, 11 = 110 ns)
DEVICE NUMBER/DESCRIPTION S29GL064N, 64 Megabit Page-Mode Flash Memory Manufactured using 110 nm MirrorBit(R) Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 7.1 S29GL064N Valid Combinations (Note 4)
S29GL064N Valid Combinations Device Number Speed Option 90 11 TFI 90 S29GL064N 11 90 90 FFI 11 V1, V2 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Notes 1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3. 2. TSOP package marking omits packing type designator from ordering part number. 3. BGA package marking omits leading S29 and packing type designator from ordering part number. 4. Contact local sales for availability for Leaded lead-frame parts. BFI 01, 02 V1, V2 03, 04 01, 02, 03, 04 LAA064 (Note 3) Fortified BGA 0, 2, 3 (Note 1) VBK048 (Note 3) Fine-pitch BGA TS056 (Note 2) TSOP Package, Material & Temperature Range Model Number 03, 04, 06, 07 TS048 (Note 2) V6, V7 TSOP Packing Type Package Description
8. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to
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S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 8.1 Device Bus Operations
DQ8-DQ15 Operation
Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Legend L = Logic Low = VIL H = Logic High = VIH VID = 11.5-12.5 V VHH = 11.5-12.5 V X = Don't Care SA = Sector Address AIN = Address In DIN = Data In DOUT = Data Out Notes 1. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.) 2. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 10.5 on page 56).
CE# L L L VCC 0.3V L X
OE# L H H X H X
WE# H L L X H X
RESET# H H H VCC 0.3V H L
WP# X (Note 1) (Note 1) X X X
ACC X X VHH H X X
Addresses AIN AIN AIN X X X
DQ0- DQ7 DOUT (Note 2) (Note 2) High-Z High-Z High-Z
BYTE# = VIH DOUT (Note 2) (Note 2) High-Z High-Z High-Z
BYTE# = VIL DQ8-DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ0-DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data on page 41 for more information. Refer to the AC Read-Only Operations table for timing specifications and the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data.
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Sheet
8.2.1
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)-A3. Address bits A2-A0 in word mode (A2-A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the read-page addresses constant and changing the intra-read page addresses.
8.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The Word Program Command Sequence on page 42 contains details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 8.2 - 8.8 indicate the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
8.3.1
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms.
8.3.2
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC or ACC pin, depending on model number, returns the device to normal operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# contains an internal pullup; when unconnected, WP# is at VIH.
8.3.3
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7- DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 29 and Autoselect Command Sequence on page 42 for more information.
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S29GL-N_01_09 November 16, 2007
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Sheet
8.4
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics on page 62 for the standby current specification.
8.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics on page 62 for the automatic sleep mode current specification.
8.6
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, Hi-Z all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS0.3 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 15.4 on page 66 for the timing diagram.
8.7
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
November 16, 2007 S29GL-N_01_09
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Data
Sheet
Table 8.2 S29GL032N (Models 01, 02, V1, V2) Sector Addresses
Sector Size (KB/ Sector A20-A15 Kwords) SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 16-bit Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 16-bit Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63
A20-A15 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
20
S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
Table 8.3 S29GL032N (Model 03) Top Boot Sector Addresses
Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 16-bit Address Range 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8-bit Address Range 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh 16-bit Address Range 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35
A20-A12 000000xxx 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx
Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
A20-A12 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 100100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
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Data
Sheet
Table 8.4 S29GL032N (Model 04) Bottom Boot Sector Addresses
Sector Size (KB/ Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 16-bit Address Range 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 16-bit Address Range E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34
A20-A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx
Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70
A20-A12 011100xxx 011101xxx 011110xxx 011111xxx 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx
22
S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
Table 8.5 S29GL064N (Models 01, 02, V1, V2) Sector Addresses (Sheet 1 of 2)
Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 16-bit Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 16-bit Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45
A21-A15 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101
Sector SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109
A21-A15 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
23
Data
Sheet
Table 8.5 S29GL064N (Models 01, 02, V1, V2) Sector Addresses (Sheet 2 of 2)
Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 16-bit Address Range 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh 16-bit Address Range 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh
Sector SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63
A21-A15 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111
Sector SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127
A21-A15 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111
Table 8.6 S29GL064N (Model 03) Top Boot Sector Addresses (Sheet 1 of 2)
Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 16-bit Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 16-bit Address Range 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22
A21-A12 0000000xxx 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx
Sector SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90
A21-A12 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx
24
S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
Table 8.6 S29GL064N (Model 03) Top Boot Sector Addresses (Sheet 2 of 2)
Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 16-bit Address Range 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8-bit Address Range 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh 7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh 16-bit Address Range 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67
A21-A12 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011100xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0101011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx 1000000xxx 1000001xxx 1000010xxx 1000011xxx
Sector SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
A21-A12 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
25
Data
Sheet
Table 8.7 S29GL064N (Model 04) Bottom Boot Sector Addresses (Sheet 1 of 2)
Sector Size (KB/ Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 530000h-53FFFFh 16-bit Address Range 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 298000h-29FFFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 690000h-69FFFFh 16-bit Address Range 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-28FFFFh 288000h-28FFFFh 290000h-297FFFh 348000h-34FFFFh
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA90
A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011100xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0100011xxx 0100100xxx 0100101xxx 1010011xxx
Sector SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA112
A21-A12 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1101001xxx
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Table 8.7 S29GL064N (Model 04) Bottom Boot Sector Addresses (Sheet 2 of 2)
Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 16-bit Address Range 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh Sector Size (KB/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8-bit Address Range 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh 16-bit Address Range 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh
Sector SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111
A21-A12 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx
Sector SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
A21-A12 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111xxx
Table 8.8 S29GL064N (Models 06, 07, V6, V7) Sector Addresses (Sheet 1 of 2)
16-bit Address Range 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 16-bit Address Range 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18
A21-A15 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010
Sector SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82
A21-A15 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010
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Table 8.8 S29GL064N (Models 06, 07, V6, V7) Sector Addresses (Sheet 2 of 2)
16-bit Address Range 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF 268000-26FFFF 270000-277FFF 278000-27FFFF 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF 2F8000-2FFFFF 16-bit Address Range 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF 300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF
Sector SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63
A21-A15 0010011 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111
Sector SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127
A21-A15 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110 1100111 1101000 1101001 1101010 1101011 1101100 1101101 1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111
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8.8
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A3, A2, A1, and A0 must be as shown in Table 8.9 on page 29. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 8.2 - Table 8.8). Table 8.9 shows the remaining address bits that are don't care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 10.1 on page 51 and Table 10.3 on page 53. This method does not require VID. Refer to the Autoselect Command Sequence section for more information. Table 8.9 Autoselect Codes, (High Voltage Method)
DQ7 to DQ0 Amax to A15 X A14 to A10 X A8 to A7 X A5 to A4 X A3 to A2 L L L L H X X VID X L X H H L L L H X X VID X L X H H L L H SA X VID X L X L DQ8 to DQ15 A1 L L H H L H H H A0 L H L H H L H L BYTE# = VIH 00 22 22 22 22 22 22 X BYTE# = VIL X X X X X X X X 01, 02 V1, V2 01h 7Eh 0Ch 01h 7Eh 1Dh 00h Model Number 03, 04 01h 7Eh 10h 00h (04, bottom boot) 01h (03, top boot) 7Eh 1Ah 00h (04, bottom boot) 01h (03, top boot) 01h (protected), 00h (unprotected) For S29GL064N and S29GL032N: L L H X X VID X L X L H H X X 9A (factory locked), 1A (not factory locked) For S29GL064N and S29GL032N: L L H X X VID X L X L H H X X 8A (factory locked), 0A (not factory locked) 06, 07, V6, V7 01h 7Eh 13h 01h
Description Manufacturer ID: Spansion Products S29GL064N Cycle 1 Cycle 2 Cycle 3 Cycle 1 Cycle 2 Cycle 3
CE# OE# WE# L L H
A9 VID
A6 L
Sector Protection Verification Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector Legend L = Logic Low = VIL H = Logic High = VIH SA = Sector Address X = Don't care
S29GL032N
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8.9
Sector Protection
The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors:
8.9.1
Persistent Sector Protection
A command sector protection method that replaces the old 12 V controlled protection method.
8.9.2
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors are permitted
8.9.3
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in the outermost sectors. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen.
8.9.4
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable nonvolatile bits that define which sector protection method is used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This permanently sets the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This permanently sets the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit is set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. The factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the ExpressFlashTM Service. Contact your sales representative for details. It is possible to determine whether a sector is protected or unprotected. See Autoselect Command Sequence on page 42 for details.
8.10
Advanced Sector Protection
Advanced Sector Protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection is a method that replaces the old 12V controlled protection method. Password Sector Protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted.
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8.11
Lock Register
The Lock Register consists of 3 bits (DQ2, DQ1, and DQ0). These DQ2, DQ1, DQ0 bits of the Lock Register are programmable by the user. Users are not allowed to program both DQ2 and DQ1 bits of the Lock Register to the 00 state. If the user tries to program DQ2 and DQ1 bits of the Lock Register to the 00 state, the device aborts the Lock Register back to the default 11 state. The programming time of the Lock Register is same as the typical word programming time without utilizing the Write Buffer of the device. During a Lock Register programming sequence execution, the DQ6 Toggle Bit I toggles until the programming of the Lock Register has completed to indicate programming status. All Lock Register bits are readable to allow users to verify Lock Register statuses. The Customer Secured Silicon Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, and Password Protection Mode Lock Bit is DQ2 are accessible by all users. Each of these bits are non-volatile. DQ15-DQ3 are reserved and must be 1's when the user tries to program the DQ2, DQ1, and DQ0 bits of the Lock Register. The user is not required to program DQ2, DQ1 and DQ0 bits of the Lock Register at the same time. This allows users to lock the Secured Silicon Sector and then set the device either permanently into Password Protection Mode or Persistent Protection Mode and then lock the Secured Silicon Sector at separate instances and time frames. Secured Silicon Sector Protection allows the user to lock the Secured Silicon Sector area Persistent Protection Mode Lock Bit allows the user to set the device permanently to operate in the Persistent Protection Mode Password Protection Mode Lock Bit allows the user to set the device permanently to operate in the Password Protection Mode Table 8.10 Lock Register
DQ15-3 Don't Care DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 Secured Silicon Sector Protection Bit
8.12
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states
Dynamically Locked Persistently Locked Unlocked The sector is protected and can be changed by a simple command A sector is protected and cannot be changed The sector is unprotected and can be changed by a simple command
To achieve these states, three types of "bits" are used:
8.12.1
Dynamic Protection Bit (DYB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYB bits are in the "unprotected state". Each DYB is individually modifiable through the DYB Set Command and DYB Clear Command. When the parts are first shipped, all of the Persistent Protect Bits (PPB) are cleared into the unprotected state. The DYB bits and PPB Lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all PPB bits are changeable. The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPB bits cleared, the DYB bits control whether or not the sector is protected or unprotected. By issuing the DYB Set and DYB Clear command sequences, the DYB bits is protected or unprotected, thus placing each sector in the protected or unprotected state. These are the socalled Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un-protected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYB bits maybe set or cleared as often as needed. The PPB bits allow for a more static, and difficult to change, level of protection. The PPB bits retain their state across power cycles because they are Non-
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Volatile. Individual PPB bits are set with a program command but must all be cleared as a group through an erase command. The PPB Lock Bit adds an additional level of protection. Once all PPB bits are programmed to the desired settings, the PPB Lock Bit may be set to the "freeze state". Setting the PPB Lock Bit to the "freeze state" disables all program and erase commands to the Non-Volatile PPB bits. In effect, the PPB Lock Bit locks the PPB bits into their current state. The only way to clear the PPB Lock Bit to the "unfreeze state" is to go through a power cycle, or hardware reset. The Software Reset command does not clear the PPB Lock Bit to the "unfreeze state". System boot code can determine if any changes to the PPB bits are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock Bit to disable any further changes to the PPB bits during system operation. The WP# write protect pin adds a final level of hardware protection. When this pin is low it is not possible to change the contents of the WP# protected sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set and DYB Clear commands for the dynamic sectors switch the DYB bits to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be disabled to the "unfreeze state" by either putting the device through a power-cycle, or hardware reset. The PPB bits can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again to the "freeze state" locks the PPB bits, and the device operates normally again. To achieve the best protection, execute the PPB Lock Bit Set command early in the boot code, and protect the boot code by holding WP# = VIL.
8.12.2
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to each sector. If a PPB is programmed to the protected state through the "PPB Program" command, that sector is protected from program or erase operations is read-only. If a PPB requires erasure, all of the sector PPB bits must first be erased in parallel through the "All PPB Erase" command. The "All PPB Erase" command preprograms all PPB bits prior to PPB erasing. All PPB bits erase in parallel, unlike programming where individual PPB bits are programmable. The PPB bits have the same endurance as the flash memory. Programming the PPB bit requires the typical word programming time without utilizing the Write Buffer. During a PPB bit programming and all PPB bit erasing sequence executions, the DQ6 Toggle Bit I toggles until the programming of the PPB bit or erasing of all PPB bits has completed to indicate programming and erasing status. Erasing all of the PPB bits at once requires typical sector erase time. During the erasing of all PPB bits, the DQ3 Sector Erase Timer bit outputs a 1 to indicate the erasure of all PPB bits are in progress. When the erasure of all PPB bits has completed, the DQ3 Sector Erase Timer bit outputs a 0 to indicate that all PPB bits have been erased. Reading the PPB Status bit requires the initial access time of the device.
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8.12.3
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. When set to the "freeze state", the PPB bits cannot be changed. When cleared to the "unfreeze state", the PPB bits are changeable. There is only one PPB Lock Bit per device. The PPB Lock Bit is cleared to the "unfreeze state" after power-up or hardware reset. There is no command sequence to unlock or "unfreeze" the PPB Lock Bit. Configuring the PPB Lock Bit to the freeze state requires approximately 100ns. Reading the PPB Lock Status bit requires the initial access time of the device. Table 8.11 Sector Protection Schemes
Protection States DYB Bit Unprotect Unprotect Unprotect Unprotect Protect Protect Protect Protect PPB Bit Unprotect Unprotect Protect Protect Unprotect Unprotect Protect Protect PPB Lock Bit Unfreeze Freeze Unfreeze Freeze Unfreeze Freeze Unfreeze Freeze Sector State Unprotected - PPB and DYB are changeable Unprotected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable Protected - PPB and DYB are changeable Protected - PPB not changeable, DYB is changeable
Table 8.11 contains all possible combinations of the DYB bit, PPB bit, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB bit is set, and the PPB Lock Bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the PPB Lock Bit to "unfreeze state". If the PPB bit is cleared, the sector can be dynamically locked or unlocked. The DYB bit then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB bit, PPB bit, and PPB Lock Bit for a given sector can be verified by writing a DYB Status Read, PPB Status Read, and PPB Lock Status Read commands to the device. The Autoselect Sector Protection Verification outputs the OR function of the DYB bit and PPB bit per sector basis. When the OR function of the DYB bit and PPB bit is a 1, the sector is either protected by DYB or PPB or both. When the OR function of the DYB bit and PPB bit is a 0, the sector is unprotected through both the DYB and PPB.
8.13
Persistent Protection Mode Lock Bit
Like the Password Protection Mode Lock Bit, a Persistent Protection Mode Lock Bit exists to guarantee that the device remain in software sector protection. Once programmed, the Persistent Protection Mode Lock Bit prevents programming of the Password Protection Mode Lock Bit. This guarantees that a hacker could not place the device in Password Protection Mode. The Password Protection Mode Lock Bit resides in the "Lock Register".
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8.14
Password Sector Protection
The Password Sector Protection method allows an even higher level of security than the Persistent Sector Protection method. There are two main differences between the Persistent Sector Protection and the Password Sector Protection methods: When the device is first powered on, or comes out of a reset cycle, the PPB Lock Bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. The only means to clear and unfreeze the PPB Lock Bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in a one-time programmable (OTP) region outside of the flash memory. Once the Password Protection Mode Lock Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear and unfreeze the PPB Lock Bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock Bit is cleared to the unfreezed state, and the PPB bits can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each password check after the valid 64-bit password is entered for the PPB Lock Bit to be cleared to the "unfreezed state". This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password.
8.15
Password and Password Protection Mode Lock Bit
In order to select the Password Sector Protection method, the customer must first program the password. The factory recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Read operations. Once the desired password is programmed in, the customer must then set the Password Protection Mode Lock Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when programming the Password Protection Mode Lock Bit. More importantly, the user must be sure that the password is correct when the Password Protection Mode Lock Bit is programmed. Due to the fact that read operations are disabled, there is no means to read what the password is afterwards. If the password is lost after programming the Password Protection Mode Lock Bit, there is no way to clear and unfreeze the PPB Lock Bit. The Password Protection Mode Lock Bit, once programmed, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Protection Mode Lock Bit is not erasable. Once Password Protection Mode Lock Bit is programmed, the Persistent Protection Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
8.16
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Password Read commands. The password function works in conjunction with the Password Protection Mode Lock Bit, which when programmed, prevents the Password Read command from reading the contents of the password on the pins of the device.
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8.17
Persistent Protection Bit Lock (PPB Lock Bit)
A global volatile bit. The PPB Lock Bit is a volatile bit that reflects the state of the Password Protection Mode Lock Bit after power-up reset. If the Password Protection Mode Lock Bit is also programmed after programming the Password, the Password Unlock command must be issued to clear and unfreeze the PPB Lock Bit after a hardware reset (RESET# asserted) or a power-up reset. Successful execution of the Password Unlock command clears and unfreezes the PPB Lock Bit, allowing for sector PPB bits to be modified. Without issuing the Password Unlock command, while asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a the "freeze state". If the Password Protection Mode Lock Bit is not programmed, the device defaults to Persistent Protection Mode. In the Persistent Protection Mode, the PPB Lock Bit is cleared to the unfreeze state after power-up or hardware reset. The PPB Lock Bit is set to the freeze state by issuing the PPB Lock Bit Set command. Once set to the freeze state the only means for clearing the PPB Lock Bit to the "unfreeze state" is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode. Reading the PPB Lock Bit requires a 200ns access time.
8.18
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. The factory offers the device with the Secured Silicon Sector either customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customerlockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the Secured Silicon Sector Indicator Bit permanently set to a 0. The factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a 1. Thus, the Secured Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector Address Range 000000h-000007h 000008h-00007Fh ExpressFlash Factory Locked ESN or determined by customer Determined by customer
Customer Lockable Determined by customer
ESN Factory Locked ESN Unavailable
The system accesses the Secured Silicon Sector through a command sequence (see Write Protect (WP/ ACC#) on page 36). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0.
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8.18.1
Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256byte Secured Silicon sector. The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions on page 41. Programming and protecting the Secured Silicon Sector must be used with caution since, once protected, there is no procedure available for unprotecting the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. The Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm. Once the Secured Silicon Sector is programmed, locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing within the remainder of the array.
8.18.2
Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h-000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices. Customers may opt to have their code programmed by the factory through the ExpressFlash service (Express Flash Factory Locked). The devices are then shipped from the factory with the Secured Silicon Sector permanently locked. Contact your sales representative for details on using the ExpressFlash service.
8.19
Write Protect (WP/ACC#)
The Write Protect function provides a hardware method of protecting the first or last sector without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. See the table in DC Characteristics on page 62. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in Sector Protection on page 30. Note that WP/ACC# contains an internal pullup; when unconnected, WP/ACC# is at VIH.
8.20
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 10.1 on page 51 and Table 10.3 on page 53 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
8.20.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
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8.20.2
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.20.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
8.20.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
9. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 9.1 on page 37 - Table 9.4 on page 40. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 9.1 on page 37 - Table 9.4 on page 40. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Alternatively, contact your sales representative for copies of these documents. Table 9.1 CFI Query Identification String
Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (x8) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 9.2 System Interface String
Addresses (x16) Addresses (x8) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0003h 0005h 0004h 0000h Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Reserved for future use Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word program 2N times typical. Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Note CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information tables to obtain the VCC range for particular part numbers. Please consult the Erase and Programming Performance table for typical timeout specifications.
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Table 9.3 Device Geometry Definition
Addresses (x16) 27h Addresses (x8) 4Eh Data 00xxh Description Device Size = 2N byte 0017h = 64 Mb, 0016h = 32 Mb Flash Device Interface description (refer to CFI publication 100) 28h 29h 2Ah 2Bh 2Ch 50h 52h 54h 56h 58h 000xh 0000h 0005h 0000h 00xxh 0001h = x16-only bus devices 0002h = x8/x16 bus devices Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 007Fh, 0000h, 0000h, 0001h = 64 Mb (01, 02, 06, 07, V1, V2, V6, V7) 0007h, 0000h, 0020h, 0000h = 64 Mb (03, 04) 003Fh, 0000h, 0000h, 0001h = 32 Mb (01, 02, V1, V2) 0007h, 0000h, 0020h, 0000h = 32 Mb (03, 04) Erase Block Region 2 Information (refer to CFI publication 100) 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 60h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 00xxh 0000h 0000h 000xh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h, 0000h, 0000h, 0000h = 64 Mb (01, 02, 06, 07, V1, V2, V6, V7) 007Eh, 0000h, 0000h, 0001h = 64 Mb (03, 04) 0000h, 0000h, 0000h, 0000h = 32 Mb (01, 02, V1, V2) 003Eh, 0000h, 0000h, 0001h = 32 Mb (03, 04)
2Dh 2Eh 2Fh 30h
5Ah 5Ch 5Eh 60h
00xxh 000xh 00x0h 000xh
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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Table 9.4 Primary Vendor-Specific Extended Query
Addresses (x16) 40h 41h 42h 43h 44h Addresses (x8) 80h 82h 84h 86h 88h Data 0050h 0052h 0049h 0031h 0033h Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required 45h 8Ah 00xxh Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit 0011h = x8-only bus devices 0010h = all other devices Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in smallest sector Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 0008h = Advanced sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 4Fh 9Eh 00xxh 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh
8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch
0002h 0001h 0000h 0008h 0000h 0000h 0002h 00B5h 00C5h
50h
A0h
0001h
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10. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 10.1 on page 51 and Table 10.3 on page 53 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
10.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 50 for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations-AC Characteristics on page 64 provide the read parameters, and Figure 15.2 on page 65 shows the timing diagram.
10.2
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erasesuspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-toBuffer-Abort Reset command sequence to reset the device for the next operation.
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10.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at specific addresses:
A7:A0 (x16) 00h 01h 0Eh 0Fh 03h (SA)02h A6:A-1 (x8) 00h 02h 1Ch 1Eh 06h (SA)04h
Identifier Code Manufacturer ID Device ID, Cycle 1 Device ID, Cycle 2 Device ID, Cycle 3 Secured Silicon Sector Factory Protect Sector Protect Verify
Note The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing on unlock cycle (two cycles). This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
10.4
Enter/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Table 10.1 on page 51 and Table 10.3 on page 53 show the address and data requirements for both command sequences. See also Secured Silicon Sector Flash Memory Region on page 35 for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
10.4.1
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10.1 on page 51 and Table 10.3 on page 53 show the address and data requirements for the word program command sequence, respectively. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device returns to the read mode, to ensure data integrity. Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the same word address multiple times without intervening erases (incremental bit programming) requires a modified programming method. For such application requirements, please contact your local Spansion representative. Word programming is supported for backward compatibility with existing Flash driver software and for occasional writing of individual words. Use of write buffer programming (see below) is strongly recommended for general programming use when more than a few words are to be programmed. The effective word programming time using write buffer programming is approximately four times shorter than the single word programming time.
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Any bit in a word cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
10.4.2
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass mode command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 10.1 on page 51 and Table 10.3 on page 53 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode.
10.4.3
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system programs six unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-A4. All subsequent address/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation aborts. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique writebuffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address is programmed. Once the specified number of write buffer locations are loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
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Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5= 0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress.This flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. For applications requiring incremental bit programming, a modified programming method is required; please contact your local Spansion representative. Any bit in a write buffer address range cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
10.4.4
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC pin depending on the particular product. When the system asserts VHH on the WP#/ACC or ACC pin. The device uses the higher voltage on the WP#/ACC or ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# contains an internal pullup; when unconnected, WP# is at VIH. Figure 10.1 on page 45 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations-AC Characteristics on page 64 for parameters, and Figure 15.3 on page 65 for timing diagrams.
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Figure 10.1 Write Buffer Programming Operation
Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1(WC) and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to flash sector address
Read DQ7 - DQ0 at Last Loaded Address
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ7 - DQ0 with address = Last Loaded Address No
Yes
(Note 2)
DQ7 = Data? No
Yes
(Note 3)
FAIL or ABORT
PASS
Notes 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. 3. If this flowchart location was reached because DQ5= 1, then the device FAILED. If this flowchart location was reached because DQ1= 1, then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1= 1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5= 1, write the Reset command. 4. See Table 10.1 on page 51 and Table 10.3 on page 53 for command sequences required for write buffer programming.
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Figure 10.2 Program Operation
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note See Table 10.1 on page 51 and Table 10.3 on page 53 for program command sequence.
10.5
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 20 s maximum and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation is suspended, the system can read array data from any non-suspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One-time Program area), then user must use the proper command sequences to enter and exit this region. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 42 for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 55 for more information. The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming.
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Figure 10.3 Program Suspend/Program Resume
Program Operation or Write-to-Buffer Sequence in Progress
Write address/data XXXh/B0h
Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations
Wait 20 s
Read data as required
Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors
No
Done reading? Yes Write address/data XXXh/30h
Write Program Resume Command Sequence
Device reverts to operation prior to Program Suspend
10.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 10.1 on page 51 and Table 10.3 on page 53 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to Write Operation Status on page 55 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If this occurs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. Figure 10.4 on page 49 illustrates the algorithm for the erase operation. Refer to Table 15.3 on page 67 for parameters, and Figure 15.7 on page 69 for timing diagrams.
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10.7
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 10.1 on page 51 and Table 10.3 on page 53 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. Figure 10.4 on page 49 illustrates the algorithm for the erase operation. Refer to Table 15.3 on page 67 for parameters, and Figure 15.7 on page 69 for timing diagrams.
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Figure 10.4 Erase Operation
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh?
Yes Erasure Completed
Notes 1. See Table 10.1 and Table 10.3 for program command sequence. 2. See the section on DQ3 for information on the sector erase timer.
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10.8
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s (maximum of 20 s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Write Operation Status on page 55 for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to Write Operation Status on page 55 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode on page 29 and Autoselect Command Sequence on page 42 sections for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip resumes erasing. During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress is impeded as a function of the number of suspends. The result is a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance is not significantly impacted.
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10.9
Command Definitions
Table 10.1 Command Definitions (x16 Mode, BYTE# = VIH)
Command Sequence (Note 1) Cycles Bus Cycles (Notes 2-5) First RA XXX 555 555 555 555 555 555 555 555 555 SA 555 555 XXX XXX 555 555 XXX XXX 55 RD F0 AA AA AA AA AA AA AA AA AA 29 AA AA A0 90 AA AA B0 30 98 2AA 2AA PA XXX 2AA 2AA 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 555 555 F0 20 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 555 SA 90 90 90 90 90 88 90 A0 25 XXX PA SA 00 PD WC PA PD WBL PD X00 X01 X01 X03 (SA)X02 0001 227E (Note 17) (Note 9) 00/01 X0E (Note 18) X0F (Note 18) Second Third Fourth Fifth Sixth
Read (Note 5) Reset (Note 6) Autoselect (Note 7) Manufacturer ID Device ID (Note 8) Device ID Secured Silicon Sector Factory Protect Sector Protect Verify (Note 10)
1 1 4 6 4 4 4 3 4 4 3 1 3 3 2 2 6 6 1 1 1
Enter Secured Silicon Sector Region Exit Secured Silicon Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 12) Unlock Bypass Unlock Bypass Program (Note 13) Unlock Bypass Reset (Note 14) Chip Erase Sector Erase Program/Erase Suspend (Note 15) Program/Erase Resume (Note 16) CFI Query (Note 17)
Legend X = Don't care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. 11. Total number of cycles in command sequence is determined by number of words written to write buffer. Maximum number of cycles in command sequence is 21, including Program Buffer to Flash command. 12. Command sequence resets device for next command after aborted writeto-buffer operation. 13. Unlock Bypass command is required prior to Unlock Bypass Program command. 14. Unlock Bypass Reset command is required to return to read mode when device is in unlock bypass mode. 15. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only during a sector erase operation. 16. Erase Resume command is valid only during Erase Suspend mode. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. 18. Refer to Table 8.9 on page 29, for individual Device IDs per device density and model number.
Notes 1. See Table 8.1 on page 17 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. During unlock and command cycles, when lower address bits are 555 or 2AA as shown in table, address bits above A11 and data bits above DQ7 are don't care. 5. No unlock or command cycles required when device is in read mode. 6. Reset command is required to return to read mode (or to erase-suspendread mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device is providing status information. 7. Fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15-DQ8 are don't care. Except for RD, PD and WC. See Autoselect Command Sequence on page 42 for more information. 8. For S29GL064N and S29GL032N, Device ID must be read in three cycles. 9. Refer to Table 8.9 on page 29 for data indicating Secured Silicon Sector factory protect status. 10. Data is 00h for an unprotected sector and 01h for a protected sector.
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Table 10.2 Sector Protection Commands (x16)
Cycles Bus Cycles (Notes 2-4) First Addr 555 XX 00 XX 555 XX XXX 00 XX 555 XX XX SA XX 555 XX XXX XX 555 XX XX SA XX Data AA A0 Data 90 AA A0 PWD0 25 90 AA A0 80 RD(0) 90 AA A0 RD(0) 90 AA A0 A0 RD(0) 90 XX 00 XX 2AA SA SA 00 55 00 01 555 E0 XX 2AA XX 00 55 00 555 50 XX 2AA PWAx 01 00 XX 2AA SA 00 00 55 PWDx PWD1 03 00 55 00 30 555 C0 02 00 PWD2 PWD0 03 01 PWD3 PWD1 02 PWD2 03 PWD3 00 29 555 60 Second Addr 2AA XXX Data 55 Data Third Addr 555 Data 40 Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data
Command Sequence (Notes) Command Set Entry (Note 5) Program (Note 6) Read (Note 6) Command Set Exit (Note 7) Command Set Entry (Note 5) Password Protection Program (Note 8) Read (Note 9) Unlock (Note 10) Command Set Exit (Note 7) Command Set Entry (Note 5) PPB Program (Note 11) All PPB Erase (Notes 11, 12) PPB Status Read Command Set Exit (Note 7) Command Set Entry (Note 5) PPB Lock Bit Set PPB Lock Bit Status Read Command Set Exit (Note 7) Command Set Entry (Note 5) DYB Set DYB Clear DYB Status Read Command Set Exit (Note 7)
3 2 1 2 3 2 4 7 2 3 2 2 1 2 3 2 1 2 3 2 2 1 2
Legend X = Don't care. RA = Address of the memory location to be read. SA = Sector Address. Any address that falls within a specified sector. See Tables 8.2-8.8 for sector address ranges. Notes 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. No unlock or command cycles required when bank is reading array data.
Volatile Sector Protection (DYB)
Global Volatile Sector Protection Freeze (PPB Lock)
Non-Volatile Sector Protection (PPB)
Lock Register Bits
PWA = Password Address. Address bits A1 and A0 are used to select each 16bit portion of the 64-bit entity. PWD = Password Data. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected, DQ0 = 1. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is required for reading password. 10. Password may be unlocked or read in any order. Unlocking requires the full password (all seven cycles). 11. ACC must be at VIH when setting PPB or DYB. 12. "All PPB Erase" command pre-programs all PPBs before erasure to prevent over-erasure.
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Table 10.3 Command Definitions (x8 Mode, BYTE# = VIL)
Cycles Bus Cycles (Notes 2-5) First Addr RA XXX AAA AAA AAA AAA AAA AAA AAA AAA AAA SA AAA AAA AAA AAA XXX XXX 1 1 1 XXX XXX AA Data RD F0 AA AA AA AA AA AA AA AA AA 29 AA AA AA AA A0 90 B0 30 98 555 555 555 555 PA XXX 55 55 55 55 PD 00 AAA AAA AAA AAA F0 80 80 20 AAA AAA AA AA 555 555 55 55 AAA SA 10 30 555 555 555 555 555 555 555 555 555 55 55 55 55 55 55 55 55 55 AAA AAA AAA AAA AAA AAA AAA AAA SA 90 90 90 90 90 88 90 A0 25 XXX PA SA 00 PD BC PA PD WBL PD X00 X02 X02 X06 (SA)X04 00/01 01 7E (Note 10) X1C (Note 17) X1E (Note 17) Second Addr Data Third Addr Data Addr Fourth Data Addr Fifth Data Addr Sixth Data
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) Device ID Secured Silicon Sector Factory Protect Sector Protect Verify (Note 11)
1 1 4 6 4 4 4 3 4 4 3 1 3 6 6
Enter Secured Silicon Sector Region Exit Secured Silicon Sector Region Program Write to Buffer (Note 12) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Chip Erase Sector Erase Unlock Bypass Unlock Bypass Program Unlock Bypass RESET Program/Erase Suspend (Note 14) Program/Erase Resume (Note 15) CFI Query (Note 16)
Legend X = Don't care RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.
PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A21-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within same write buffer page as PA. BC = Byte Count. Number of write buffer locations to load minus 1. 10. Refer to Table 8.9 on page 29, for data indicating Secured Silicon Sector factory protect status. 11. Data is 00h for an unprotected sector and 01h for a protected sector. 12. Total number of cycles in command sequence is determined by number of bytes written to write buffer. Maximum number of cycles in command sequence is 37, including Program Buffer to Flash command. 13. Command sequence resets device for next command after aborted writeto-buffer operation. 14. System may read and program in non-erasing sectors, or enter autoselect mode, when in Erase Suspend mode. Erase Suspend command is valid only during a sector erase operation. 15. Erase Resume command is valid only during Erase Suspend mode. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. 17. Refer to Table 8.9 on page 29, for individual Device IDs per device density and model number.
Notes 1. See Table 8.1 on page 17 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. All others are write cycles. 4. During unlock and command cycles, when lower address bits are 555 or AAA as shown in table, address bits above A11 are don't care. 5. Unless otherwise noted, address bits A21-A11 are don't cares. 6. No unlock or command cycles required when device is in read mode. 7. Reset command is required to return to read mode (or to erase-suspendread mode if previously in Erase Suspend) when device is in autoselect mode, or if DQ5 goes high while device is providing status information. 8. Fourth cycle of autoselect command sequence is a read cycle. Data bits DQ15-DQ8 are don't care. See Autoselect Command Sequence on page 42 for more information. 9. For S29GL064N and S29GL032A Device ID must be read in three cycles.
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Table 10.4 Sector Protection Commands (x8)
Command Sequence (Notes) Command Set Entry (Note 5) Program (Note 6) Read (Note 6) Command Set Exit (Note 7) Command Set Entry (Note 5) Program (Note 8) Read (Note 9) Unlock (Note 10) Command Set Exit (Note 7) Command Set Entry (Note 5) PPB Program (Note 11) All PPB Erase (Notes 11, 12) PPB Status Read Command Set Exit (Note 7) Command Set Entry (Note 5) PPB Lock Bit Set PPB Lock Bit Status Read Command Set Exit (Note 7) Command Set Entry (Note 5) DYB Set DYB Clear DYB Status Read Command Set Exit (Note 7) 1st/8th Addr Data AAA XXX 00 XXX AAA XXX 00 07 00 05 XX AAA XXX XXX SA XXX AAA XXX XXX XXX AAA XXX XXX SA XXX AA A0 Data 90 AA 2nd/9th Addr Data 555 XXX 55 Data Bus Cycles (Notes 2-5) 3rd/10th 4th/11th 5th Addr Data Addr Data Addr Data AAA 40 Cycles 6th Addr Data 7th Data
Addr
3 2 1 2 3 2 8 11 2 3 2 2 1 2 3 2 1 2 3 2 2 1 2
Lock Register Bits
XXX 555
00 55 PWDx PWD1 03 PWD6 00 55 00 30 AAA C0 AAA 60
A0 PWAx PWD0 01 PWD7 25 00 PWD5 06 90 AA A0 80 RD(0) 90 AA A0 RD(0) 90 AA A0 A0 RD(0) 90 XX 555 SA SA XXX 555 XXX XX 555 SA 00
Password Protection
02 00 07
PWD2 PWD0 PWD7
03 01 00
PWD3 PWD1 29
04 02
PWD4 PWD2
05 03
PWD5 PWD3
06 04
PWD6 PWD4
Non-Volatile Sector Protection (PPB)
00 55 00 AAA 50
Global Volatile Sector Protection Freeze (PPB Lock)
00 55 00 01 AAA E0
Volatile Sector Protection (DYB)
XXX
00
Legend X = Don't care. RA = Address of the memory location to be read. SA = Sector Address. Any address that falls within a specified sector. See Tables 8.2-8.8 for sector address ranges. Notes 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don't cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. No unlock or command cycles required when bank is reading array data.
PWA = Password Address. Address bits A1 and A0 are used to select each 16bit portion of the 64-bit entity. PWD = Password Data. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected, DQ0 = 1. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is required for reading password. 10. Password may be unlocked or read in any order. Unlocking requires the full password (all seven cycles). 11. ACC must be at VIH when setting PPB or DYB. 12. "All PPB Erase" command pre-programs all PPBs before erasure to prevent over-erasure.
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10.10 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 10.5 on page 60 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or is completed.
10.11 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 appears on successive read cycles. Table 10.5 on page 60 shows the outputs for Data# Polling on DQ7. Figure 10.5 on page 56 shows the Data# Polling algorithm. Figure 15.8 on page 69 shows the Data# Polling timing diagram.
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Figure 10.5 Data# Polling Algorithm
START
Read DQ15-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ15-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
10.12 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 10.5 on page 60 shows the outputs for RY/BY#.
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Sheet
10.13 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 55). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 10.5 on page 60 shows the outputs for Toggle Bit I on DQ6. Figure 10.6 on page 58 shows the toggle bit algorithm. Figure 15.9 on page 70 shows the toggle bit timing diagrams. Figure 15.10 on page 70 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II on page 58.
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Figure 10.6 Toggle Bit Algorithm
START
Read DQ7-DQ0
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See the subsections on DQ6 and DQ2 for more information.
10.14 DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10.5 on page 60 to compare outputs for DQ2 and DQ6.
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Figure 10.6 on page 58 shows the toggle bit algorithm in flowchart form. Figure 15.9 on page 70 shows the toggle bit timing diagram. Figure 15.10 on page 70 shows the differences between DQ2 and DQ6 in graphical form.
10.15 Reading Toggle Bits DQ6/DQ2
Refer to Figure 10.6 on page 58 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 10.6 on page 58).
10.16 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5 produces a 1. In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
10.17 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10.5 on page 60 shows the status of DQ3 relative to the other status bits.
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10.18 DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data. See Write Buffer on page 18 for more details. Table 10.5 Write Operation Status
Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm ProgramSuspend Read EraseSuspend Read Program-Suspended Sector Non-Program Suspended Sector Erase-Suspended Sector Non-Erase Suspended Sector DQ7# DQ7# DQ7# Toggle Toggle Toggle 1 No toggle DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A RY/BY# 0 0 1 1 N/A Toggle N/A 1 1 N/A N/A N/A N/A N/A N/A N/A 0 1 0 0 0
Invalid (not allowed) Data 0 Data 0 0 0
Program Suspend Mode
Erase Suspend Mode
Erase-Suspend-Program (Embedded Program) Write-toBuffer Busy (Note 3) Abort (Note 4)
Notes 1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to 1 when the device aborts the write-to-buffer operation.
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11. Absolute Maximum Ratings
Parameter Rating
Storage Temperature, Plastic Packages Ambient Temperature with Power Applied VCC (Note 1) Voltage with Respect to Ground A9, OE#, ACC and RESET# (Note 2) All other pins (Note 1) Output Short Circuit Current (Note 3)
-65C to +150C -65C to +125C -0.5 V to +4.0 V -0.5 V to +12.5 V -0.5 V to VCC+0.5 V 200 mA
Notes 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 11.2. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is -0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 11.1. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 11.1 Maximum Negative Overshoot Waveform
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
Figure 11.2 Maximum Positive Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
12. Operating Ranges
Parameter Ambient Temperature (TA), Industrial (I) Devices Supply Voltages VCC for full voltage range VIO Notes 1. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. VIO input voltage always must be lower than VCC input voltage. Range -40C to +85C +2.7 V to +3.6 V +1.65 to +3.6 V
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13. DC Characteristics
Table 13.1 DC Characteristics, CMOS Compatible
Parameter Symbol ILI ILIT ILO Parameter Description (Notes) Input Load Current (Note 1) A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH, VCC = VCC max, f = 1 MH ICC1 VCC Initial Read Current (Note 1) CE# = VIL, OE# = VIH, VCC = VCC max, f = 5 MHz CE# = VIL, OE# = VIH, VCC = VCC max, f = 10 MHz CE# = VIL, OE# = VIH, VCC = VCC max f = 10 MHz CE# = VIL, OE# = VIH, VCC = VCC max f = 33 MH CE# = VIL, OE# = VIH, VCC = VCC max VCC = VCC max; VIO = VCC; OE# = VIH; VIL = (VSS+0.3V) / -0.1V; CE#, RESET# = VCC 0.3 V VCC = VCCmax, VIO = VCC, VIL = (VSS+0.3V) / -0.1V; RESET# = VSS 0.3 V VCC = VCCmax, VIO = VCC, VIH = VCC 0.3 V; VIL = (VSS+0.3V) / -0.1V; WP#/ACC = VIH CE# = VIL, OE# = VIH, VCC = VCCmax, WP#/ACC = VIH WP#/ ACC VCC -0.1 0.7 VIO VCC = 2.7 -3.6 V VCC = 2.7 -3.6 V IOL = 100 A IOH = -100 A 0.85 VIO 2.3 2.5 11.5 11.5 6 25 45 1 5 50 Min Typ Max #WP/ACC: 2.0 A Others: 1.0 A 35 1.0 10 30 50 10 mA 20 60 mA mA Unit A A A
ICC2
VCC Intra-Page Read Current (Note 1)
ICC3 ICC4
VCC Active Erase/Program Current (Notes 2, 3) VCC Standby Current
1
5
A
ICC5
VCC Reset Current
1
5
A
ICC6
Automatic Sleep Mode (Note 4)
1
5
A
IACC VIL VIH VHH VID VOL VOH1 VOH2 VLKO
ACC Accelerated Program Current Input Low Voltage 1 (Note 5) Input High Voltage 1 (Note 5) Voltage for ACC Erase/Program Acceleration Voltage for Autoselect Output Low Voltage (Note 5) Output High Voltage (Note 5) Low VCC Lock-Out Voltage (Note 3)
10 50
20 60 0.3 x VIO VIO + 0.3 12.5 12.5 0.15 x VIO
mA mA V V V V V V V
Notes 1. ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase, Embedded Program, or Write Buffer Programming is in progress. 3. Not 100% tested. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 5. VIO = 1.65-1.95 V or 2.7-3.6 V. 6. VCC = 3 V and VIO = 3 V or 1.8 V. When VIO is at 1.8 V, I/Os cannot operate at 3 V.
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14. Test Conditions
Figure 14.1 Test Setup
3.3 V
2.7 k Device Under Test CL 6.2 k
Note Diodes are IN3064 or equivalent.
Table 14.1 Test Specifications
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0 or VIO 0.5 VIO 0.5 VIO All Speeds 1 TTL gate pF ns V V V Unit
14.1
Key to Switching Waveforms
Waveform Inputs Steady Outputs
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Figure 14.2 Input Waveforms and Measurement Levels
VCC 0.0 V
Input
0.5 VIO
Measurement Level
0.5 VIO
Output
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15. AC Characteristics
Table 15.1 Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE tPACC tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Page Access Time CE#, OE# = VIL OE# = VIL VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V VIO = VCC = 3 V VIO = 1.8 V, VCC = 3 V Test Setup Min Max Max Max Speed Options 90 90 90 90 25 -- 25 -- 20 20 0 0 10 110 110 110 110 25 30 25 30 Unit ns ns ns ns
Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Output Enable Hold Time (Note 1) Read Toggle and Data# Polling
Max Max Max Min Min Min
ns ns ns ns ns ns
tOEH
Notes 1. Not 100% tested.
2. See Figure 14.1 on page 63 and Table 14.1 on page 63 for test specifications.
Figure 15.1 VCC Power-up Diagram
tVCS VCC VCC min
VIH RESET# tRH CE#
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Figure 15.2 Read Operation Timings
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 15.3 Page Read Timings
A23-A2
Same Page
A1-A0*
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Qa
Qb
Qc
Qd
Note * Figure shows device in word mode. Addresses are A1-A-1 for byte mode.
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Table 15.2 Hardware Reset (RESET#)
Parameter JEDEC Std. tReady tReady tRP tRH tRPD tRB
Note Not 100% tested.
Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Input Low to Standby Mode (See Note) RY/BY# Output High to CE#, OE# pin Low Max Max Min Min Min Min
All Speed Options 20 500 500 50 20 0
Unit s ns ns ns s ns
Figure 15.4 Reset Timings
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE# tRH
RESET# tRP
Notes 1. Not 100% tested. 2. See the Erase And Programming Performance on page 73 for more information. 3. For 1-16 words/1-32 bytes programmed.
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Table 15.3 Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tCEPH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time CE# High during toggle bit polling OE# High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) tWHWH1 tWHWH1 Single Word Program Operation (Note 2) Accelerated Single Word Program Operation (Note 2) tWHWH2 tWHWH2 tVHH tVCS tBUSY Notes 1. Not 100% tested. 2. See the Erase And Programming Performance on page 73 for more information. 3. For 1-16 words/1-32 bytes programmed. 4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes (that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately after programming resumes. See Figure 15.5 on page 68. Sector Erase Operation (Note 2) VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) WE# High to RY/BY# Low Description Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Min Min Min 90 Speed Options 90 90 0 15 45 0 35 0 20 20 0 0 0 35 30 240 60 54 0.5 250 50 110 sec ns s ns s 110 110 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Figure 15.5 Program Operation Timings
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tWPH
Read Status Data (last two cycles)
PA
PA
tCH
tWHWH1 Status DOUT tRB
A0h
VCC tVCS
Notes 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 15.6 Accelerated Program Timing Diagram
VHH HH
ACC
VIL or VIH IL IH tVHH VHH tVHH VHH
VIL or VIH IL IH
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Figure 15.7 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
Notes 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 55.) 2. Illustration shows device in word mode.
tRB
Figure 15.8 Data# Polling Timings (During Embedded Algorithms)
tRC Addresses tPOLL CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA tACC tCE
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
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Figure 15.9 Toggle Bit Timings (During Embedded Algorithms)
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6 / DQ2 Valid Data
Valid Status
tAS
tCEPH
tCE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 15.10 DQ2 vs. DQ6 Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
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Table 15.4 Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC Std. Description Speed Options 90 110 Unit
tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2
tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 tRH
Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Single Word Program Operation (Note 2) Accelerated Single Word Program Operation (Note 2) Sector Erase Operation (Note 2) RESET# High Time Before Write
Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Min
90 0 45 45 0 0 0 0 35 30 240 60 54 0.5 50
110
ns ns ns ns ns ns ns ns ns ns
s
sec ns
Notes 1. Not 100% tested. 2. See the Erase And Programming Performance on page 73 for more information. 3. For 1-16 words/1-32 bytes programmed. 4. If a program suspend command is issued within tPOLL, the device requires tPOLL before reading status data, once programming resumes (that is, the program resume command is written). If the suspend command was issued after tPOLL, status data is available immediately after programming resumes. See Figure 15.11 on page 72.
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Figure 15.11 Alternate CE# Controlled Write (Erase/Program) Operation Timings
PBA for program 2AA for erase SA for program buffer to flash SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
PBD for program 55 for erase 29 for program buffer to flash 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Illustration shows device in word mode.
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16. Erase And Programming Performance
Parameter Sector Erase Time S29GL032N Chip Erase Time Total Write Buffer Program Time (Notes 3, 5) Total Accelerated Effective Write Buffer Program Time (Notes 4, 5) Chip Program Time S29GL032N S29GL064N S29GL064N Typ (Note 1) 0.5 32 64 240 200 31.5 63 Max (Note 2) 3.5 64 128 s sec Unit Comments Excludes 00h programming prior to erasure (Note 6) Excludes system level overhead (Note 7)
sec
Notes 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0V, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90C; Worst case VCC, 100,000 cycles. 3. Programming time (typ) is 15 s (per word), 7.5 s (per byte). 4. Accelerated programming time (typ) is 12.5 s (per word), 6.3 s (per byte). 5. Write buffer Programming time is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10.1 on page 51 and Table 10.3 on page 53 for further information on command definitions.
Table 16.1 TSOP Pin and BGA Package Capacitance
Parameter Symbol CIN COUT CIN2 CIN3
Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
Parameter Description Input Capacitance VIN = 0
Test Setup TSOP BGA TSOP BGA TSOP BGA TSOP BGA
Typ 6 TBD 6 TBD 6 TBD 27 TBD
Max 10 TBD 12 TBD 10 TBD 30 TBD
Unit pF pF pF pF pF pF pF pF
Output Capacitance
VOUT = 0 VIN = 0 VIN = 0
Control Pin Capacitance
#RESET, #WP/ACC Pin Capacitance
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17. Physical Dimensions
17.1 TS048--48-Pin Standard Thin Small Outline Package (TSOP)
STANDARD PIN OUT (TOP VIEW) A2 2
1 N
0.10 C
-A-
SEE DETAIL B
-BE5 e
N 2
N +1 2
9 A1 C SEATING PLANE A
0.08MM (0.0031") M C A-B S
D1 D
5 4
B B
SEE DETAIL A
7
b
6
7 WITH PLATING
(c)
c1
b1
R c
GAGE LINE
e/2
BASE METAL
SECTION B-B
0
PARALLEL TO SEATING PLANE
0.25MM (0.0098") BSC
-X-
L
X = A OR B
DETAIL A
DETAIL B
Package Jedec Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MIN
TS 048 MO-142 (B) EC MAX 1.20 0.15 0.05 1.05 1.00 0.95 0.20 0.23 0.17 0.27 0.22 0.17 0.16 0.10 0.21 0.10 19.80 20.00 20.20 18.30 18.40 18.50 11.90 12.00 12.10 0.50 BASIC 0.70 0.50 0.60 3 5 0 0.20 0.08 48 NOM
NOTES:
1 2 3 4
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). NOT APPLICABLE. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15MM (.0059") PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3325 \ 16-038.10a
5 6
7 8 9
74
S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
17.2
TS056--56-Pin Standard Thin Small Outline Package (TSOP)
2X 0.10
2X (N/2 TIPS)
STANDARD PIN OUT (TOP VIEW) 2
1 N
2X 0.10 A2
0.10 REVERSE PIN OUT (TOP VIEW) 3
1 N
A
SEE DETAIL B
B
E5
N 2
N +1 2
e 9 A1 C SEATING PLANE
0.08MM (0.0031") M C A-B S
N 2 N +1 2
D1 D 0.25
2X (N/2 TIPS)
5 4
B
A
B
SEE DETAIL A
b
6
7 WITH PLATING
7
(c)
c1
b1 SECTION B-B
R (c)
GAUGE PLANE
BASE METAL
e/2
PARALLEL TO SEATING PLANE
C
0.25MM (0.0098") BSC
X X = A OR B
L
DETAIL A
Package Jedec Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MIN TS 056 MO-142 (D) EC MAX 1.20 0.15 0.05 1.05 1.00 0.95 0.20 0.23 0.17 0.27 0.22 0.17 0.16 0.10 0.21 0.10 19.80 20.00 20.20 18.30 18.40 18.50 13.90 14.00 14.10 0.50 BASIC 0.70 0.50 0.60 8 0 0.20 0.08 56 NOM
DETAIL B
NOTES:
1 2 3 4
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3356 \ 16-038.10c
5 6
7 8 9
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
75
Data
Sheet
17.3
VBK048--Ball Fine-pitch Ball Grid Array (BGA) 8.15x 6.15 mm Package
0.10 (4X)
D
A
D1
6 5
e
7
4 3 2 1 H G F E D C B A
E
SE
E1
PIN A1 CORNER
INDEX MARK
B
6
b
0.08 M C 0.15 M C A B
SD
7
A1 CORNER
10
TOP VIEW
BOTTOM VIEW
A A1
SEATING PLANE
A2
0.10 C
C
0.08 C
SIDE VIEW
NOTES: PACKAGE JEDEC VBK 048 N/A 8.15 mm x 6.15 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.35 MIN --0.18 0.62 NOM ------8.15 BSC. 6.15 BSC. 5.60 BSC. 4.00 BSC. 8 6 48 --0.80 BSC. 0.40 BSC. --0.43 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25 \ 10.05.04
76
S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
17.4
LAA064--64-Ball Fortified Ball Grid Array (BGA) 13 x 11 mm Package
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
77
Data
Sheet
18. Revision History
Section Revision 01 (February 12, 2007) Initial release. Revision 02 (February 26, 2007) Global Page Mode Read Erase And Programming Performance Revision 03 (March 15, 2007) Connection Diagrams Revision 04 (July 6, 2007) Ordering Information Sector Addresses table TSOP Pin and BGA Package Capacitance Revision 05 (August 10, 2007) Ordering Information CFI Table Revision 06 (September 18, 2007) Global Change document status to Full Production Removed 70ns access speed Removed leaded parts Altered Erase Block Region 1 & 2 Removed regulated VCC range and replaced 90 ns with 110 ns for low VIO option Added Note 4 to PACKAGE MATERIAL SET Standard option Corrected a table Added values for TSOP 64-ball Fortified BGA (LAA 064) figure: Changed inputs for balls F1 and F7. Replaced LAE064 package with LAA064. Corrected bit ranges in first paragraph. Modified maximum sector erase time in table. Description
Command Definitions (x16 mode) Table Corrected addresses for Program operation Command Definitions (x8 mode) Table Revision 07 (October 22, 2007) Global Primary Vendor-Specific Extended Query Table Revision 08 (November 2, 2007) Primary Vendor-Specific Extended Query Table S29GL064N (Model 04) Bottom Boot Sector Addresses Table Revision 09 (November 16, 2007) Erase and Program Operations Table Changed tDS from 45 ns to 35 ns Updated the data of CFI address 2D hex thru 34 hex. Updated S29GL064N (Model 04) Bottom Boot Sector Addresses Removed VID (12V) Sector protect & unprotect features Updated the data of CFI address 45hex Corrected addresses for Program operation
78
S29GL-N MirrorBit(R) Flash Family
S29GL-N_01_09 November 16, 2007
Data
Sheet
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2007 Spansion Inc. All rights reserved. Spansion(R), the Spansion Logo, MirrorBit(R), MirrorBit(R) EclipseTM, ORNANDTM, HD-SIMTM and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit(R) Flash Family
79

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